This invention pertains to a type of semiconductor integrated circuit that contains a functional circuit made of CMOS transistors, such as a logic circuit for performing the prescribed logic operation. In particular, this invention pertains to a type of semiconductor integrated circuit that can be determined to be defective or not by means of the Iddq test.
For a low threshold voltage transistor that is formed with a threshold voltage lower than the conventional voltage node, its leakage current is nevertheless larger than that of the conventional transistor although it is appropriate for performing the low voltage operation. Consequently, power consumption in the standby mode is a problem. In the prior art, various systems have been proposed in order to solve this problem. Among them, there is the system that makes use of the multi-threshold voltage CMOS (MT-CMOS) transistor which has two or more types of transistors having different threshold voltages corresponding to the operation requests.
In this system, the circuit portion that is required to perform high speed operation is composed of transistors having a low threshold voltage, and a transistor with a high threshold voltage is set as a switching transistor for lessening the generation of the leakage current in the standby mode. On the other hand, the circuit portion that is required to perform the operation at the normal operation speed is composed of transistors having the normal threshold voltage, and it is possible to minimize the leakage current in the standby mode without using a transistor for switching. Consequently, this multi-threshold voltage system is an effective technology for the semiconductor integrated circuit that can operate at a low power source voltage and can realize high speed operation and low power consumption at a low voltage.
However, for the aforementioned conventional multi-threshold voltage system, the Iddq test method has not been established. For the manufactured semiconductor integrated circuits, it is necessary to perform the test individually. Consequently, it is hard to use this system for mass production.
In order to solve this problem, a technology has been proposed to enable embodiment of the Iddq test by means of the multi-threshold voltage transistor and by exploiting the bulk bias effect of the transistor.
However, in this technology, it is necessary to generate the bulk voltages for PMOS transistors and NMOS transistors, respectively. In order to generate these voltages, it is necessary to form a dedicated voltage generating circuit, such as a booster circuit, on the chip. In order to lessen the leakage current in the standby mode, even in the standby state, it is necessary to have the booster circuit operate so that the bulk bias voltage is kept being fed. As a result, not only the layout area of the semiconductor integrated circuit is increased, but also the power consumption due to the booster circuit in the standby mode becomes a problem.
The purpose of this invention is to solve the aforementioned problems of the conventional methods by providing a type of semiconductor integrated circuit which can lessen the increase in the circuit area to the necessary minimum level and can lessen the leakage current in the standby mode, and which does not need the reliability test, such as the test, etc., when Iddq test is performed to determine whether it is defective or not.
In accordance with one aspect of this invention provides a type of semiconductor integrated circuit characterized by the following facts: the semiconductor integrated circuit has a functional circuit, which has a transistor of the first electroconductive type and a transistor of the second electroconductive type having low threshold voltages and connected between a first voltage node and a second voltage node, and which performs the prescribed signal processing with respect to the input signal, and a switching circuit, which has a transistor having the normal threshold voltage and connected between a first power source voltage feeding terminal and said first voltage node or between said second voltage node and a second power source voltage feeding terminal, and which feeds the driving current selectively with respect to said functional circuit; in normal operation, said first power source voltage and second power source voltage are applied to the channel region of said transistor of the first electroconductive type and said transistor of the second electroconductive type, respectively; in the test operation, a first bias voltage higher than the first power source voltage and a second bias voltage lower than the second power source voltage are applied to the channel region of said transistor of the first electroconductive type and said channel region of said transistor of the second electroconductive type, respectively.
Also, in a preferable scheme of this invention, it has a bias voltage application means which applies said first bias voltage and said second bias voltage or the first power source voltage and the second power source voltage on said wiring for the first bias voltage and said wiring for the second bias voltage, respectively.
Also, in a preferable scheme of this invention, it has a bias voltage application means which applies said first bias voltage and said second bias voltage or the first power source voltage and the second power source voltage to said wiring for the first bias voltage and said wiring for the second bias voltage, respectively.
Also, the channel region of the transistor that forms said switching circuit is connected to the channel region of said transistor of the first electroconductive type or the channel region of said transistor of the second electroconductive type.
Also, said first bias voltage and said second bias voltage are fed from an IC tester or other peripheral equipment.